Improved Floating Point Multiplier Design based on Canonical Sign Digit
Published at : 27 Jan 2014
Volume : IJtech
Vol 5, No 1 (2014)
DOI : https://doi.org/10.14716/ijtech.v5i1.150
Saha, P., Bhattacharyya, P., Dandapat, A., 2014. Improved Floating Point Multiplier Design based on Canonical Sign Digit. International Journal of Technology. Volume 5(1), pp. 22-31
| P. Saha | Department of Electronics and Communication Engineering, National Institute of Technology, Shillong, Meghalaya-793003, India |
| P. Bhattacharyya | Department of Electronics and Telecommunication Engineering, Bengal Engineering and Science University. Shibpur, Howrah-711103, India |
| A. Dandapat | Department of Electronics and Communication Engineering, National Institute of Technology, Shillong, Meghalaya-793003, India |
Improved floating point (FP) multiplier based on canonical signed digit code (CSDC) has been reported in this paper. Array structure was implemented through Hatamain’s scheme of partial product generation along with Baugh-Wooley’s (B.W) sign digit multiplication technique. Moreover, CSDC approaches were used for the addition of partial products in constant time without carry propagation and independent of operands. The functionality of these circuits was checked and performance parameters, such as propagation delay, dynamic switching power consumptions were calculated by spice spectre using 90nm CMOS technology. Implementation methodology ensures the stage reduction for floating point multiplier, hence substantial reduction in propagation delay compared with B.W.’s methodology, has been investigated. Implementation result offered propagation delay of the single precision floating point multiplier was only ~14.7ns propagation delay while the power consumption of the same was ~23.7mW. Almost ~40% improvement in speed from earlier reported FP multiplier, e.g. B.W implementation methodology, the best architecture reported so far, has been achieved.
Baugh-Wooley (B.W) multiplier, CSD adder, CSD multiplier, High Speed
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