• International Journal of Technology (IJTech)
  • Vol 5, No 1 (2014)

Improved Floating Point Multiplier Design based on Canonical Sign Digit

Improved Floating Point Multiplier Design based on Canonical Sign Digit

Title: Improved Floating Point Multiplier Design based on Canonical Sign Digit
P. Saha , P. Bhattacharyya, A. Dandapat

Corresponding email:

Published at : 27 Jan 2014
Volume : IJtech Vol 5, No 1 (2014)
DOI : https://doi.org/10.14716/ijtech.v5i1.150

Cite this article as:
Saha, P., Bhattacharyya, P., Dandapat, A., 2014. Improved Floating Point Multiplier Design based on Canonical Sign Digit. International Journal of Technology. Volume 5(1), pp. 22-31

P. Saha Department of Electronics and Communication Engineering, National Institute of Technology, Shillong, Meghalaya-793003, India
P. Bhattacharyya Department of Electronics and Telecommunication Engineering, Bengal Engineering and Science University. Shibpur, Howrah-711103, India
A. Dandapat Department of Electronics and Communication Engineering, National Institute of Technology, Shillong, Meghalaya-793003, India
Email to Corresponding Author

Improved Floating Point Multiplier Design based on Canonical Sign Digit

Improved floating point (FP) multiplier based on canonical signed digit code (CSDC) has been reported in this paper. Array structure was implemented through Hatamain’s scheme of partial product generation along with Baugh-Wooley’s (B.W) sign digit multiplication technique. Moreover, CSDC approaches were used for the addition of partial products in constant time without carry propagation and independent of operands. The functionality of these circuits was checked and performance parameters, such as propagation delay, dynamic switching power consumptions were calculated by spice spectre using 90nm CMOS technology. Implementation methodology ensures the stage reduction for floating point multiplier, hence substantial reduction in propagation delay compared with B.W.’s methodology, has been investigated. Implementation result offered propagation delay of the single precision floating point multiplier was only ~14.7ns propagation delay while the power consumption of the same was ~23.7mW. Almost ~40% improvement in speed from earlier reported FP multiplier, e.g. B.W implementation methodology, the best architecture reported so far, has been achieved.

Baugh-Wooley (B.W) multiplier, CSD adder, CSD multiplier, High Speed


Avizienis, A., 1961. Signed-digit Number Representations for Fast Parallel Arithmetic. IRE Transaction on Electronics Computer, Volume EC-10, pp. 389–400 http://dx.doi.org/10.1109/tec.1961.5219227

Baugh, C.R., Wooley, B.A., 1973. A Two’s Complement Parallel Array Multiplication Algorithm. IEEE Transaction on Computer, Volume C-22, pp. 1045–1047 http://dx.doi.org/10.1109/t-c.1973.223648

Das, S.K., Pinotti, M.C., 1996. Fast VLSI Circuits for CSD Coding and GNAF coding. Electronics Letters, Volume 32, pp. 632–634 http://dx.doi.org/10.1049/el:19960449

Hao, Z.-G., Zeng, X.-J., Li, G.-K., 2005. The CMOS Circuit Design of a High-Speed Floating-Point Multiplier. Computer Engineering & Science,Volume 21, pp.54–57

Hatamian, M., 1986. A 70-MHz 8-bit × 8-bit Parallel Pipelined Multiplier in 2.5-?m CMOS. IEEE Journal on Solid-State Circuits, Volume 21, pp. 505–513 http://dx.doi.org/10.1109/jssc.1986.1052564

Hickmann, B., Krioukov, A., Schulte, M., 2007. A Parallel IEEE P754 Decimal Floating-Point Multiplier. Proceedings of IEEE 25th International conference on computer design. Lake Tahoe, CA, 7-10th Oct, pp. 296–303 http://dx.doi.org/10.1109/iccd.2007.4601916

IEEE Standard 754 for Binary Floating-Point Arithmetic, 1996

Koren, I., 1993. Computer Arithmetic Algorithms, Prentice Hall

Lim, Y.C., Evans, J.B., Liu, B., 1991. Decomposition of Binary Integers into Signed Power-of-two Terms. IEEE Transaction on Circuits and Systems, Volume 38, pp. 667–672 http://dx.doi.org/10.1109/31.81865

Quach, N.T., Takagi,N., Flynn, M.J., 2004. Systematic IEEE Rounding Method for High-Speed Floating-Point Multipliers. IEEE Transaction on Very Large Scale Integration (VLSI) Systems, Volume 12, pp. 511–521 http://dx.doi.org/10.1109/tvlsi.2004.825860

Raafat, R., Amira, M., Majeed, A., Samy R., 2008. A Decimal Fully Parallel and Pipelined Floating Point Multiplier. Proceedings of IEEE 42nd Asilomar Conference on Signals, Systems and Computers, Pacific Grove, CA, 26-29th Oct, pp. 1800–1804 http://dx.doi.org/10.1109/acssc.2008.5074737

Renxi, G., Shangjun Z., Hainan Z., Xiaobi M.,Wenying G., Lingling X.,Yang, H., 2009. Hardware Implementation of a High Speed Floating Point Multiplier based on FPGA. Proceedings of IEEE 4th International Conference on Computer Science & Education, Nanning, 25-28th July, pp. 1902–1906 http://dx.doi.org/10.1109/iccse.2009.5228240

Saha, P., Banerjee, A., Dandapat, A., Bhattacharyya, P., 2011. ASIC Implementation of High Speed Processor for Calculating Discrete Fourier Transformation using Circular Convolution Technique. International Journal of World Scientific and Engineering Academy and Society (WSEAS), Volume 10, pp. 278–288

Saha, P.K, Banerjee, A., Dandapat, A., 2009. High Speed Low Power Complex Multiplier Design using Parallel Adders and Subtractors. International Journal on Electronic and Electrical Engineering, (IJEEE),Volume 07, pp. 38–46

Takagi, N., Yasuura, H., Yajima, S., 1985. High-Speed VLSI Multiplication Algorithm with a Redundant Binary Addition Tree. IEEE Transaction on Computer, Volume C-34, pp. 789–796 http://dx.doi.org/10.1109/tc.1985.1676634

Uya, M., Kaneko, K., Yasui, J., 1984. A CMOS Floating Point Multiplier. IEEE Journal of Solid State Circuits, Volume Sc-9, pp. 697–702 http://dx.doi.org/10.1109/jssc.1984.1052210

Uyemura, J.P., 2001. CMOS Logic Circuit Design, Kluwer Academic Publishers.http://dx.doi.org/10.1007/b117409

Wanhammar, L., 1999. DSP Integrated Circuits” PP- 479, Academic Press. http://dx.doi.org/10.1016/b978-012734530-7/50001-5

Wu, J., Ying, Z., 2005. Design of High Speed Floating-multiplier, Journal of Circuits and Systems, Volume 10, pp.6–11

Zhao, Z.-W., Chen, H., Han, Y.-Q., 2004. Design of High-performance 32-bit Floating-point Multipliers for ASIC. Systems Engineering and Electronics, Volume 26, pp.531–534

Zhou, D.-J., Sun, Feng., Yu, Z.-G., 2007. Design of a 32-bit High-Speed Floating-Point Multiplier. Semiconductor Technology, Volume 20, pp.871–874