• Vol 9, No 1 (2018)
  • Electrical, Electronics, and Computer Engineering

VLSI Circuit Optimization for the 8051 MCU

Kim Ho Yeap, Kang Wei Thee, Koon Chun Lai, Humaira Nisar, K. Chandrasekaran Krishnan


Publish at : 27 Jan 2018 - 09:03
IJtech : IJtech Vol 9, No 1 (2018)
DOI : https://doi.org/10.14716/ijtech.v9i1.798

Cite this article as:
Yeap, K.H., Thee, K.W., Lai, K.C., Nisar, H., Krishnan, K.C., 2018. VLSI CIRCUIT OPTIMIZATION FOR THE 8051 MCU. International Journal of Technology. Volume 9(1), pp. 142-149
31
Downloads
Kim Ho Yeap Universiti Tunku Abdul Rahman
Kang Wei Thee Universiti Tunku Abdul Rahman
Koon Chun Lai Universiti Tunku Abdul Rahman
Humaira Nisar Universiti Tunku Abdul Rahman
K. Chandrasekaran Krishnan Universiti Tunku Abdul Rahman
Email to Corresponding Author

Abstract
image

With the aid of Electronic Design Automation tools, we perform circuit optimization on the 8051 microcontroller. The original 8051 microcontroller operates at a clock frequency 12 MHz, and it was designed based on 3.5-µm process technology. Hence, the device is slow and the chip size is large. To enhance the performance of the device and to minimize the die size, we used 90-nm technology in our design. We first performed optimization when mapping the RTL codes with the 90 nm standard cell libraries. Once the gate level netlist was generated, we developed the layout of the device by going through floor-planning, placement, and routing. We show that our new design is capable of operating at 150 MHz (i.e., 12.5 times faster than the original design), with a significant reduction in chip size (i.e., the total area is 77249.814850 µm2). The power consumption of the chip is 593.9899 µW, which is at least 32% lower than that of other 8051 derivatives.


Floor-planning; Physical design; Placement; Routing; Synthesis

Conclusion

In this paper, we have shown that the design of the original 8051 microcontroller can be significantly enhanced. By synthesizing the RTL code using libraries with the technology size half of its original and by carefully designing its VLSI layout with the aid of Synopsys EDA tools, we were able to increase the clock frequency to 150 MHz and reduce the die size to 77249.814850 µm2. The power consumption of our chip is 593.9899 µW, which is found to be at least 32% lower than that of the existing 8051 derivatives.

References

Ahmad, I., Ho, Y.K., Majlis, B.Y., 2006. Fabrication and Characterization of a 0.14 ?m CMOS Device using ATHENA and ATLAS Simulators. Semiconductor Physics, Quantum Electronics & Optoelectronics, Volume 9(2), pp. 40–44

Arsalan, S., 2013. Sun Tracking System with Microcontroller 8051. International Journal of Scientific and Engineering Research, Volume 4(6), pp. 2998–3001

Chang, K.L., Chang, J.S., Gwee, B.H., Chong, K.S., 2013. Synchronous-logic and Asynchronous-logic 8051 Microcontroller Cores for Realizing the Internet of Things: A Comparative Study on Dynamic Voltage Scaling and Variation Effects. IEEE Journal on Emerging and Selected Topics in Circuits and Systems, Volume 3(1), pp. 23–34

Iozzi, F., Saponara, S., Morello, A.J., Fanucci, L. 2005. 8051 CPU Core Optimization for Low Power at Register Transfer Level. 2005 PhD Research in Microelectronics and Electronics, July, Volume 2, pp. 178–181

Jain, G., Noorani, N., Badole, V., 2013. Design and Implementation of a GPS Receiver using 8051 Microcontroller. International Journal of Research in Advent Technology, Volume 1(5), pp. 1–7

Kanniga, E., Sundararajan, M., 2015. Design of 8051 Microcontroller Based Security System with a Laser Beam Network. Indian Journal of Science and Technology, Volume 8(31), pp. 1–3

Li, Y., Lian, Y., Perez, V. 2009. Design Optimization for an 8-bit Microcontroller in Wireless Biomédical Sensors. In: Proceedings of the 2009 IEEE Biomedical Circuits and Systems Conference, 26-28 November, pp. 33–36

Oregano System., 2013. 8051 IP Core. Available online at: http://www.oreganosystems.at

Pahuja, R., Kumar, N., 2014. Android Mobile Phone Controlled Bluetooth Robot using 8051 Microcontroller. International Journal of Scientific Engineering and Research, Volume 2(7), pp. 14–17

Sai, V., Mickle, M.H., 2013. Low Power 8051-MISA-based Remote Execution Unit Architecture for IoT and RFID Applications. International Journal of Circuits and Architecture Design, Volume 1(1), pp. 4–19

Saponara, S., Fanucci, L., Morello, A.J. 2004. Power Optimization of Digital IP Macrocells for Embedded Controls Systems. In: Proceedings of the 2004 IEEE International Conference on Industrial Technology, December, Vol. 3, pp.1617–1620

Sung, R., Bendix, P., Das, M.B., 1998. Extraction of High-frequency Equivalent Circuit Parameters of Submicron Gate-length MOSFET’s. IEEE Transactions on ElectronDevices, Volume 45(8), pp. 1769–1775

Synopsys, Inc., 2007. Training & Education. Available online at: http://training.synopsys.com