• Vol 9, No 1 (2018)
  • Electrical, Electronics, and Computer Engineering

VLSI Circuit Optimization for the 8051 MCU

Kim Ho Yeap, Kang Wei Thee, Koon Chun Lai, Humaira Nisar, K. Chandrasekaran Krishnan

Publish at : 27 Jan 2018 - 09:03
IJtech : IJtech Vol 9, No 1 (2018)
DOI : https://doi.org/10.14716/ijtech.v9i1.798

Cite this article as:
Yeap, K.H., Thee, K.W., Lai, K.C., Nisar, H., Krishnan, K.C., 2018. VLSI CIRCUIT OPTIMIZATION FOR THE 8051 MCU. International Journal of Technology. Volume 9(1), pp. 142-149
Kim Ho Yeap Universiti Tunku Abdul Rahman
Kang Wei Thee Universiti Tunku Abdul Rahman
Koon Chun Lai Universiti Tunku Abdul Rahman
Humaira Nisar Universiti Tunku Abdul Rahman
K. Chandrasekaran Krishnan Universiti Tunku Abdul Rahman
Email to Corresponding Author


With the aid of Electronic Design Automation tools, we perform circuit optimization on the 8051 microcontroller. The original 8051 microcontroller operates at a clock frequency 12 MHz, and it was designed based on 3.5-µm process technology. Hence, the device is slow and the chip size is large. To enhance the performance of the device and to minimize the die size, we used 90-nm technology in our design. We first performed optimization when mapping the RTL codes with the 90 nm standard cell libraries. Once the gate level netlist was generated, we developed the layout of the device by going through floor-planning, placement, and routing. We show that our new design is capable of operating at 150 MHz (i.e., 12.5 times faster than the original design), with a significant reduction in chip size (i.e., the total area is 77249.814850 µm2). The power consumption of the chip is 593.9899 µW, which is at least 32% lower than that of other 8051 derivatives.

Floor-planning; Physical design; Placement; Routing; Synthesis


In this paper, we have shown that the design of the original 8051 microcontroller can be significantly enhanced. By synthesizing the RTL code using libraries with the technology size half of its original and by carefully designing its VLSI layout with the aid of Synopsys EDA tools, we were able to increase the clock frequency to 150 MHz and reduce the die size to 77249.814850 µm2. The power consumption of our chip is 593.9899 µW, which is found to be at least 32% lower than that of the existing 8051 derivatives.


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