• Vol 5, No 2 (2014)
  • Electrical, Electronics, and Computer Engineering

Design and Simulation of Two Bits Single-electron Logic Circuit using Double Quantum Dot Single Electron Transistor

Arief Udhiarto, Mohammad Ali Tamam, Ratno Nuryadi, Djoko Hartanto


Cite this article as:
Udhiarto, A., Tamam, M.A., Nuryadi, R., Hartanto, D., 2014. Design and Simulation of Two Bits Single-electron Logic Circuit using Double Quantum Dot Single Electron Transistor. International Journal of Technology. Volume 5(2), pp. 152-158
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Arief Udhiarto Electrical Engineering Department, Faculty of Engineering, Universitas Indonesia, Kampus Baru UI Depok 16424, Indonesia
Mohammad Ali Tamam Electrical Engineering Department, Faculty of Engineering, Universitas Indonesia, Kampus Baru UI Depok 16424, Indonesia
Ratno Nuryadi Center for Material Technology, Agency for the Assessment and Application of Technology, Puspitek Building 224, South Tangerang 15314, Indonesia
Djoko Hartanto Electrical Engineering Department, Faculty of Engineering, Universitas Indonesia, Kampus Baru UI Depok 16424, Indonesia
Email to Corresponding Author

Abstract
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Electrons in a single electron transistor (SET) are transported one by one from source to drain based on the coulomb blockade mechanism. The transport rate is sensitively influenced by the presence of event a single electron charge located near the quantum dot. Based on this characteristic, we propose a Double Quantum Dot (DQD) SET to manipulate the presence of an electron in Quantum Dot (QD) as an implementation of a single-electron logic concept. The existence of an electron in the QD is used to represent logic 0 (no electron in QD) or logic 1 (an electron in QD). The logic states are sensed by a SET charge detector. Design of circuit based on DQD and SET charge detector are simulated by using SIMON 2.0 software. From the simulation, we have successfully developed a two-bit logic circuit by controlling the presence of an electron in DQD. We found that the existence of an electron in QD can be controlled by application of a gate voltage larger than 190µV. Gate should be separated from QD by a non-tunnel capacitor of 500 aF. No larger than 1 aF of interdot tunnel capacitance is required to isolate the QD from one to another. The existence of an electron in QD is successfully detected by SET based charge detector.

Charge Detector, Double Quantum Dot (DQD), Single-Electron Logic, Single Electron Transistor (SET), Software SIMON 2.0

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